Multistage Yield Prediction Across Wafer Fabrication, Assembly, and Final Testing Processes

Abstract

Semiconductor yield depends on connected changes that occur across wafer fabrication, assembly, and final testing. Yield loss may begin during wafer processing, increase during package assembly, and become visible only during final electrical screening. This article presents a multistage yield prediction framework that combines process data, inspection records, assembly indicators, and final test outcomes to estimate final manufacturing yield. The method uses cleaned stage-wise data, engineered risk features, and supervised machine learning to compare single-stage and multistage prediction approaches. Wafer fabrication variables identify early process risk, assembly variables capture package-related stress, and final testing variables confirm accumulated device failure. The results show that predicted yield decreases across the manufacturing route, while the multistage model gives higher accuracy than single-stage models. The framework supports earlier warning, better lot review, and faster engineering action. It can help semiconductor manufacturers reduce late-stage rejection and improve production control in high-volume advanced production environments today.